Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices including a three-dimensional 3D array.
Description of Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin-film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
Another structure that provides vertical NAND strings in a charge trapping memory technology is described in Katsumata, et al., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009. The structure described in Katsumata et al. includes vertical NAND gates, using dielectric charge trapping technology to create a storage site at each gate/vertical channel interface. The memory structure can be arranged as a straight vertical NAND with a column of semiconductor material arranged as the vertical channel for the NAND gate, with a lower select gate for connection to a common source line adjacent the substrate, and an upper select gate on top for connection to bit lines. A plurality of horizontal word lines is formed using planar word line layers that intersect with the columns, forming so-called gate-all-around cells. Alternatively, the memory structure of Katsumata et al. can be arranged so that two adjacent columns of gate-all-around cells are connected at the bottom to form a U-shaped NAND string, in which a first select gate on top of one column acts as a string select gate, and a second select gate on top of the adjacent column acts as a ground select gate. See also, Komori et al., “Disturbless Flash Memory due to High Boost Efficiency on BiCS Structure and Optimal Memory Film Stack for Ultra High Density Storage Device,” Electron Devices Meeting IEDM December 2008.
Other approaches have included vertical gate technologies, such as have been described in U.S. Pat. No. 8,503,213, entitled Memory Architecture Of 3D Array With Alternating Memory String Orientation And String Select Structures, issued 6 Aug. 2013 by inventors Chen et al.
For conventional NAND Flash architecture, the “block” is defined by a physical grouping including the NAND strings configured between a set of bit lines (BLs) and a common source line (CSL) with a set of intersecting word lines (WLs). See, U.S. Patent Application Pub. No. 2013/0279251, entitled “Novel Shielding 2-Cycle Half-Page Read And Program Schemes For Advanced Nand Flash Design,” published 24 Oct. 2013, by inventor Lee. In a NAND flash, each NAND string includes a first switch, often called a string select switch, for connecting a selected NAND string to a corresponding bit line, and a second switch, often called a ground select switch, for connecting a selected NAND string to a common source line. The common source line is referred to herein as a reference line RL in view of the fact that it can be biased to act either as a source or drain depending on the biasing arrangement applied. The second switch in this configuration is referred to herein as a reference select switch, in view of the fact that the reference line to which it connects the NAND strings can be biased in a number of ways other than simply ground.
The control signals for the string select switch and reference select switch on each NAND string present a structural complexity in 3D structures. For example, NAND strings in a block that share a bit line must be at least one SSL for each. The control signal for the second switch is often called the ground select line GSL, and is referred to herein as a reference select line RSL. Blocks of NAND strings have been configured in the prior art in which all of the second switches share a single RSL. This reduces the complexity of the reference select line RSL structure substantially, and reduces the amount of signal wiring required in the memory.
In typical operation, the erase (ERS) unit usually corresponds to a block, which is the so-called “block erase.” During ERS operations, the WLs that intersect the block are applied the same bias, and in the substrate well on which the memory block is implemented in a 2D array, the bit lines and the common reference line are appropriately biased to cause the threshold voltage (Vt) of all cells in the same block to be lowered below an erase threshold level. A block erase typically erases all of the NAND strings which share a common reference select line RSL and are therefore connected to the common reference line RL as a unit. As a result, the biasing arrangements available for erase are limited by the structure which requires the same common source line bias to be applied to all of the NAND strings in the block.
For a given chip capacity, a larger block size (ERS unit) means a smaller number of blocks in the array arrangement. However, some memory management operations, such as garbage collection and wear leveling, operate on erase block units. A small number of large blocks can enlarge the time used for block level memory management. A smaller number of large blocks for a given memory capacity may require more operations for memory management on each block. Also, the memory management routines that operate on block boundaries can require erase and program operations to move data around, and the program and erase cycling consumes the cycling endurance of the memory cells. Therefore, the block size can directly affect performance of the product in a number of ways.
Some ways to address the problems related to the size of an erase block are described in commonly owned, and co-pending U.S. patent application Ser. No. 14/643,907, entitled “Forced-Bias Method In Sub-Block Erase,” filed 13 Mar. 2015 by inventors Kuo-Pin Chang, Hang-Ting Lue and Wen-Wei Yeh (MXIC 2148-1); and commonly owned, and co-pending U.S. patent application Ser. No. 14/668,728, entitled “Page Erase In Flash Memory,” filed 25 Mar. 2015 by inventor Kuo-Pin Chang (MXIC 2149-1); which applications are incorporated by reference as if fully set forth herein.
It can be desirable therefore to provide architectures and operating methods for 3D memories which do not sacrifice memory capacity, while supporting a smaller erase unit.